Papers of 1999
(1) N. Yoshikawa, C. Fukuzato and M. Sugahara, "Single Electron Transfer Logic Gate Family", Jpn. J. Appl. Phys. 38 (1999) pp. 433-438.
(2) N. Yoshikawa, H. Tago and K. Yoneyama, "A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3161-3164.
(3) N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "Simulation and 18 Gb/s Testing of a Data-Driven Self-Timed RSFQ Demultiplexer", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.4349-4352.
(4) L. Zheng, N. Yoshikawa, Z. J. Deng, X. Meng, S. R. Whiteley and T. Van Duzer, "20 GHz RSFQ Multiplexer and Demultiplexer", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3310-3313.
(5) Z. J. Deng, N. Yoshikawa, S. R. Whiteley and T. Van Duzer, "Self-Timing and Vector Processing in RSFQ Digital Circuit Technology", IEEE Trans. Appl. Superconductivity, vol. 9, March, 1999, pp.7-17.
(6) N. Yoshikawa and J. Koshiyama, "A Cell-Based Design Approach for RSFQ Circuits using Binary Decision Diagram", Superconductor Science and Technology, vol. 12, 1999, pp.918-920.
(7) N. Yoshikawa and Y. Kato, "Reduction of Power Consumption of RSFQ Circuits by Inductance-Load-Biasing", Superconductor Science and Technology, vol. 12, 1999, pp.782-785.
Other Years