International Conf. of 2010
(1) N. Yoshikawa, H. Suzuki, K. Taketomi, and Y. Yamanashi, “Development of SFQ Logic Gates Connectable to Passive Transmission Lines and Their Application to Digital Signal Processors,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, A02-2, pp.16-20.
(2) T. Sugiura, Y. Yamanashi, and N. Yoshikawa, “Demonstration of 30 GHz generation of truly random numbers using superconductive circuit,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P1, pp.38-40.
(3) Y. Yamanashi, I. Okawa, and N. Yoshikawa, “Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P3, pp.45-46.
(4) D. Ozawa, Y. Natsume, Y. Yamanashi, and N. Yoshikawa, “Design and Evaluation of Multi-Flux Drivers Using High b鐶 Junctions,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P4, pp.47-48.
(5) T. Xue, P. Heejoung, Y. Yamanashi, and N. Yoshikawa, “Effect of Parasitic Inductance and Capacitance on the Stability of Josephson Latching Drivers,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P6, pp.51-52.
(6) K. Minami, Y. Yamanashi, and N. Yoshikawa, “Design of a single-flux quantum majority logic gate,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P9, pp.59-60.
(7) T. Shimojima, Y. Yamanashi, and N. Yoshikawa, “Consideration of a digital SQUID with positive magnetic feedback,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P10, pp.61-62.
(8) Y. Natsume, D. Ozawa, Y. Yamanashi, and N. Yoshikawa, “SFQ Chip-to-Chip Communication using Inductive Coupling,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P11, pp.63-64.
(9) H. Suzuki, Y. Yamanashi, and N. Yoshikawa, “Design of a 2 x 2 switch using PTL-connectable logic cells,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P12, pp.65-66.
(10) Y. Okamoto, H. Park, H. Jin, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, “Access Time Measurement of 64 kb Josephson/CMOS Hybrid Memories by using SFQ Time-to-Digital Converter,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P13, pp.67-70.
(11) Y. Takahashi, H. Suzuki, Y. Yamanashi, and N. Yoshikawa, “Design of Input Circuits for SFQ Multi-Stop Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P14, pp.71-72.
(12) S. Miura, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Improvement of SFQ Circuit Systems for Measuring Escape Rates of Josephson Junctions,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P20, pp.86-88.
(13) N. Takeuchi, D. Ozawa, S. Miura, Y. Yamanashi, and Y. Yoshikawa, “Design of RSFQ Circuits for Controlling Superconducting Quantum Bits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P21, pp.89-94.
(14) Y. Arita, Y. Yamanashi, T. Baba, and N. Yoshikawa, “Integrating optical waveguides with SFQ circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13 , 2010, P22, pp.95-97.
(15) T. Kainuma, F. Miyaoka, Y. Shimamura, Y. Yamanashi, and N. Yoshikawa, “Proposal of Resettable Muller-C gates Using Single-Flux-Quantum Circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P23, pp.98-99.
(16) K. Yaguchi, Y. Okamoto, H. Jin, H. Park, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, "Implementation of a Self-Bias Circuit for Josephson-CMOS Hybrid Memories" Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P24, pp.100-102.
(17) H. Jin, Y. Okamoto, H. Park, K. Yaguchi, Y. Yamanashi, and N. Yoshikawa, “Investigation of High-Speed CMOS Differential Amplifier for Josephson/CMOS Hybrid Memory Systems,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P27, pp.107-108.
(18) Y. Shimamura, T. Kainuma, F. Miyaoka, H. Park, Y. Yamanashi, and N. Yoshikawa, “Design of an SFQ Half-Precision Floating-Point Multipliers Using 10 kA/cm2 Nb Multi- Layer Process,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P28, pp.109-110.
(19) M. Tanaka, H. Akaike, A. Fujimaki, Y. Yamanashi, N. Yoshikawa, S. Nagasawa, K. Takagi, and N. Takagi, “100-GHz single-flux-quantum bit-serial adder based on 10-ka/cm2 niobium process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 4, 2010, 3EY-01.
(20) Y. Shimamura, K. Toshiki, F. Miyaoka, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, and K. Takagi, “50 GHz operation of SFQ floating-point multiplier using 10 kA/cm^2 Nb process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-01.
(21) N. Yoshikawa, and D. Ozawa “Adiabatic quantum flux parametron as an ultra-low-power superconducting logic device,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 4, 2010, 3EB-06.
(22) T. Sugiura, Y. Yamanashi, and N. Yoshikawa, “Demonstration of 30 Gbit/s generation of superconductive true random number generator,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-04.
(23) T. Kainuma, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, and K. Takagi, “Design and implementation of component circuits of an SFQ half-precision floating-point adder using 10 kA/cm2 Nb process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-06.
(24) D. Ozawa, Y. Natsume, Y. Yamanashi, and N. Yoshikawa, “Design and Implementation of Multi-flux drivers using High Beta_c Junctions,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-01.
(25) Y. Yamanashi, I. Okawa, and N. Yoshikawa, “Design approach of dynamically reconfigurable single flux quantum logic gates,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-07.
(26) F. Miyaoka, T. Kainuma, Y. Shimamura, Y. Yamanashi, and N. Yoshikawa, “High-speed test of a radix-2 butterfly processing element for the Fast Fourier Transform using SFQ circuits,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-05.
(27) K. Yaguchi, Y. Okamoto, H. Jin, H. Park, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, “Implementation of Josephson-CMOS hybrid memories with bit-serial data input/output ports,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-02.
(28) Y. Arita, N. Yoshikawa, T. Baba, and Y. Yamanashi, “Integration of optical waveguides with SFQ circuits,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-03.
(29) H. Jin, Y. Okamoto, K. Yaguchi, Y. Yamanashi, and N. Yoshikawa, “Investigation of characteristic variations of high-speed cryo CMOS amplifiers for interface circuits of the Josephson/CMOS hybrid memories,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-05.
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