Dept. of Electrical and Computer Engin., Yokohama National Univ.



International Conf.

Domestic Conf.

(1) N. Yoshikawa, H. Tago and K. Yoneyama, "Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits", IEICE Transactions on Electronics vol. E81-C, No. 10 October 1998, pp. 1618 - 1626.

(2) N. Yoshikawa, H. Tago and K. Yoneyama, "A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3161-3164.

(3) Z. J. Deng, H. Zhang, N. Yoshikawa, U. Ghoshal, E. Fang, A. Flores, L. Zheng, S. R. Whiteley and T. Van Duzer, "Memory-Processor Interface with Hybrid CMOS-RSFQ Technology", Applied Superconductivity, vol. 6, pp. 355-360, 1998.

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