Dept. of Electrical and Computer Engin., Yokohama National Univ.



International Conf.

Domestic Conf.

(1) A. Fujimaki, Y. Takai and N. Yoshikawa, "High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology", IEICE Transactions on Electronics, vol. E85-C, No. 3, 2002, pp. 612-616.

(2) F. Matsuzaki, K. Yoda, J. Koshiyama, K. Motoori and N. Yoshikawa, "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology", IEICE Transactions on Electronics, vol. E85-C, No. 3, 2002, pp. 659-664.

(3) N. Yoshikawa, K. Yoda, H. Hoshina and F. Matsuzaki, "Cell-Based Design Methodology for BDD RSFQ Logic Circuits -Tolerance of Basic Cells to Circuit Parameter Variations", Supercond. Sci. Technol., vol. 15, 2002, pp. 156-160.

(4) T. Van Duzer, L. Zheng, X. Meng, C. Loyo, S.R. Whiteley, L. Yu, N. Newman, J.M. Rowell, N. Yoshikawa, "Engineering issues in high-frequency RSFQ circuits", Physica C 372-376, 2002, pp. 1-6.

(5) N. Yoshikawa, F. Matsuzaki, N. Nakajima and K. Yoda, "Design and Component Test of a 1-bit RSFQ Microprocessor", Physica C 378-381, 2002, pp. 1454-1460.

(6) K. Fujiwara, H. Hoshina, J. Koshiyama, and N. Yoshikawa, "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories", Physica C378-381, 2002, pp. 1475-1480.

(7) 吉川信行, "SFQ/半導体ハイブリッドメモリー", 応用物理, 第71巻, 第1号, 2002, pp. 76-77.

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