Papers of 2003
(1) N. Yoshikawa, F. Matsuzaki, N. Nakajima, K. Fujiwara, K. Yoda and K. Kawasaki, "Design and Component Test of a Tiny Processor based on the SFQ Technology", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.441-445.
(2) N. Yoshikawa, K. Yoda, H. Hoshina, K. Kawasaki, K. Fujiwara, F. Matsuzaki, and N. Nakajima, "Cell Based Design Methodology for BDD SFQ Logic Circuits: a High Speed Test and Feasibility for Large Scale Circuit Applications," IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.523-526.
(3) K. Fujiwara, H. Hoshina, Y. Yamashiro, N. Yoshikawa, "Design and Component Test of SFQ Shift Register Memories", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.555-558.
(4) Y.J. Feng, X. Meng, S. R. Whiteley, T. Van Duzer, K. Fujiwara, H. Miyakawa, N. Yoshikawa, "Josephson-CMOS hybrid memory with ultra-high-speed interface circuit", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.467-470.
(5) F. Matsuzaki, N. Yoshikawa, M. Tanaka, A. Fujimaki, Y. Takai, "A Behavioral-Level HDL Description of SFQ Logic Circuits for Quantitative Performance Analysis of Large-Scale SFQ Digital Systems", Physica C 392-396, 2003, pp.1467-1471.
(6) K. Fujiwara, H. Miyakawa, N. Yoshikawa, Y. Feng, S.R. Whiteley, T. Van Duzer, "Implementation and Low Speed Test of Ultra-Fast Interface Circuits for Josephson-CMOS Hybrid Memories", Physica C 392-396, 2003, pp. 1495-1500.
(7) M. Tanaka, T. Kondo, A. Sekiya, A. Fujimaki, H. Hayakawa, F. Matsuzaki, N. Yoshikawa, H. Terai, S. Yorozu, "Component test toward single-flux-quantum processors", Physica C 392-396, 2003, pp. 1490-1494.
(8) H. Terai, Y. Kameda, S. Yorozu, A. Kawakami, N. Yoshikawa and Z. Wang, "High-speed testing of tandem-Banyan network switch component", Physica C 392-396, 2003, pp. 1485-1489.
(9) S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, A. Fujimaki and N. Yoshikawa, "Single flux quantum circuit technology innovation for backbone router applications", Physica C 392-396, 2003, pp.1478-1484.
(10) N. Harada, N. Yoshikawa, K. Yoda, A. Yoshida and N. Yokoyama, "Logic Operation at 5 Gbps of an Output Interface for Single Flux Quantum Systems", IEEE Trans. Applied Superconductivity, vol. 13, September, 2003, pp.3814-3817.
(11) K. Kawasaki, K. Yoda, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu, "Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram," Supercond. Sci. Technol. 16 (2003) pp. 1497-1502.
(12) K. Fujiwara, Y. Yamashiro, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, "Design and high-speed test of 4 x 8-bit SFQ shift register files," Supercond. Sci. Technol. 16 (2003) pp. 1456-1459.
(13) T. Hanai, T. Matsumoto, S. Yorozu, Y. Kameda, H. Terai, N. Yoshikawa, A. Fujimaki and H. Hayakawa, "Design of the speedup buffer for the single-flux-quantum network switch," Supercond. Sci. Technol. 16 (2003) pp. 1452-1455.
(14) M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, H. Terai, S. Yorozu, N. Yoshikawa, A. Fujimaki and H. Hayakawa, "Prototypic design of the single-flux-quantum microprocessor, CORE1," Supercond. Sci. Technol. 16 (2003) pp. 1460-1463.
(15) H. Terai, S. Yorozu, A. Fujimaki, N. Yoshikawa and Z. Wang, "A new design approach based on a multi-wiring-layer process for high-density SFQ circuits," Supercond. Sci. Technol. 16 (2003) pp. 1464-1469.
Other Years