International Conf. of 2001
(1) N. Yoshikawa, H. Miyakawa, K. Motoori, T. Van Duzer and S. Whiteley, "Josephson-CMOS Hybrid Memory Using Three-Transistor DRAM Cell", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 29-30.
(2) K. Fujiwara, J. Koshiyama and N. Yoshikawa, "Design and Test of RSFQ High-Speed Packet Switches", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 163-164.
(3) F. Matsuzaki, K. Yoda, J. Koshiyama, K. Motoori and N. Yoshikawa, "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 165-166.
(4) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(5) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(6) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(7) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(8) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(9) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
Other Years