International Conf. of 2017

(1) N. Yoshikawa, T. Igarashi, G. Konno, T. Takahashi, Y. Yamanashi, “Recent research development of memories for single-flux-quantum computing systems,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-3.

(2) N. Takeuchi, S. Nagasawa, F. China, T. Ando, M. Hidaka, Y. Yamanashi, N. Yoshikawa, “Adiabatic quantum-flux-parametron cell library developed using a 10 kA cm−2 niobium fabrication process,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-6.

(3) T. Igarashi, H. Suzuki, Y. Yamanashi, N. Yoshikawa, “Design and evaluation of loop drivers for SFQ memory cells and decoders,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-7.

(4) Q. Xu, Y. Murai, R.Saito, C. L. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “An EDA flow for AQFP VLSI design with customized interface to Cadence tools,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-8.

(5) H. Takayama, N. Tsuji, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Simulation of 4-bit random access memory cells composed of quantum flux parametron,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-9.

(6) Y. Yamanashi, Y. Ito, N. Takeuchi, N. Yoshikawa, “Investigation of reconfigurable superconducting reversible login gate,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-13.

(7) Y. Abe, K.Sano, N. Zen, G. Fujii, Y. Mawatari, Y. Yamanashi, N. Yoshikawa, “Study on the detection of single flux quantum in superconducting nano strip line,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-19.

(8) K.Sano, Y. Abe, Y. Yamanashi, N. Yoshikawa, “Measurement and evaluation of bias margins of driver/receiver circuits for current recycling technique,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-21.

(9) N. Tsuji, N. Takeuchi, C. Ayala, Y. Yamanashi, and N. Yoshikawa, “Design and implementation of scalable register files using adiabatic quantum flux parametron logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Fr-C-NJD-02.

(10) R. Sato, T. Ono, Y. Yamanashi, and N. Yoshikawa, “(Invited) Design and high speed demonstration of an SFQ complex event detector circuit for complex event processing,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Fr-I-DIG-03.

(11) Y. Xing, N. Takeuchi, K. Fang, Y. Yamanashi, and N. Yoshikawa, “Design and Demonstration of Power Divider for Adiabatic Quantum-Flux-Parametron Logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-01.

(12) Y. Yamanashi, A. Sugiyama, N. Yoshikawa, “Analog Circuit Simulator for Superconducting Circuits Containing pi-Josephson Junctions,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-13.

(13) C. L. Ayala, Q. Xu, Y. Murai, R. Saito, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, “A Large-Scale Design Flow for Adiabatic Quantum-Flux-Parametron Circuits with Retiming and Fan-out Deconstruction,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-14.

(14) Q. Xu, R. Saito, Y. Murai, C. L. Ayala, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Performance Analysis of Synthesized Benchmark Circuits Implemented in Adiabatic Superconductor Logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-15.

(15) Y. Yamanashi, H. Imai, N. Yoshikawa, “Influences of Magnetic Flux Trapped in Moats on Superconducting Integrated Circuit Operation,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-02.

(16) F. China, N. Tsuji, T. Ando, H. Takayama, N. Takeuchi, S. Nagasawa, M. Hidaka, Y. Yamanashi, and N. Yoshikawa, “High-density Integration of Adiabatic Quantum-Flux-Parametron Circuits by Using Double-Active-Layered Niobium Process,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-04.

(17) T. Matsushima, Y. Yamanashi, N. Takeuchi, N. Yoshikawa, and T. Ortlepp, “Analysis of Relationship between Gray Zone and Energy Dissipation of Adiabatic Quantum Flux Parametron,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-18.

(18) K. Sano, M. Suzuki, M. Tanaka, A. Fujimaki, N. Yoshikawa, “Fabricaton of NbTiN nanocryotrons for Josephson-CMOS hybrid memory application,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-C-HYB-04.

(19) N. Yoshikawa, “(Invited) Status of RSFQ developments in Japan,” International Workshop on Superconducting Quantum Technology, Freyburg/Unstrut, Germany, Jun. 18-21, 2017.

(20) N. Yoshikawa, “Adiabatic quantum flux parametron as an ultra-energy-efficient readout circuit for superconducting sensor arrays, ” International Workshop on Superconducting Quantum Technology, Freyburg/Unstrut, Germany, Jun. 18-21, 2017.

(21) N. Yoshikawa, “(Invited) Recent research developments of adiabatic quantum-flux-parametron circuits technology toward energy-efficient high-performance computing, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-01.

(22) Y. Abe, K. Sano, N. Zen, G. Fujii, Y. Mawatari, Y. Yamanashi, N. Yoshikawa, “Direct Detection of Single Flux Quantum Generated in Superconducting Strip Photon Detectors, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-05.

(23) T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Theory and experimental analysis of the sensitivity of an adiabatic quantum flux parametron, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-02.

(24) Q. Xu, C. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and implementation of AQFP-based register files for an AQFP 4-bit RISC microprocessor prototype, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 1EP1-12.

(25) C. Ayala, Q. Xu, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Microarchitectures for energy-efficient computing implemented in adiabatic quantum-flux-parametron logic, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 1EP1-06.

(26) N. Takeuchi, C. Ayala, Q. Xu, Y. Yamanashi, N. Yoshikawa, “(Invited) Current Progress in Adiabatic Quantum Flux Parametron, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. ED5-1-INV.

(27) Y. Tomitsuka, Y. Abe, Y. Yamanashi, N. Zen, M.Ohkubo, N. Yoshikawa, “Demonstration of picosecond time resolution of double-oscillator time-to-digital converters using single-flux-quantum circuits, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. ED5-4.

(28) H. Takayama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “A random-access-memory cell based on quantum flux parametron with three control lines, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-3.

(29) T. Matsushima, Y. Yamanashi, N. Takeuchi, N. Yoshikawa, “Proposal of superconducting analog to digital converter using quantum flux parametron, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-4.

(30) A. Sanada, Y. Yamanashi, N. Yoshikawa, “Study on Integer-Number Parallel Divider Based on Single Flux Quantum Logic, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-5.

(31) C. Ayala, Q. Xu, R. Saito, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design of an arithmetic logic unit and a data shifter for adiabatic quantum-flux-parametron-based microprocessor, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-6.

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