International Conf. of 2015

(1) N. Yoshikawa, “(keynote) Ultra-energy-efficient adiabatic superconducting logic: what is the minimum energy limit in computation?”, 2015 Joint UK-Japan Workshop on Physics and Applications of Superconductivity, University of Cambridge, Cambridge, UK, April 12-15, 2015.

(2) T. Ono, Y. Yamanashi , N. Yoshikawa, “Design of a Complex Event Detector Circuit for Complex Event Processing System Using SFQ Circuits,” Superconducting SFQ VLSI Workshop (SSV 2015), Nagoya, JAPAN, July 10, 2015, Oral-4.

(3) C. L. Ayala, N. Takeuchi, Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Towards VLSI Adiabatic Quantum-Flux-Parametron Logic Circuits,” Superconducting SFQ VLSI Workshop (SSV 2015), Nagoya, JAPAN, July 10, 2015, SS-2.

(4) T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi , N. Yoshikawa, “(Invited) Demonstration of 10k gate-scale adiabatic-quantumflux-parametron circuits,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P04-INV.

(5) Y. Sakashita, T. Ono, Y. Yamanashi1, N. Yoshikawa, “Design and High-Speed Component Tests of an SFQ FFT Processor using the 10 kA/cm2 Advanced Process,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O03.

(6) K. Sano, Y. Muramatsu, T. Shimoda, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration of a Superconducting Time-of-Flight Mass Spectrometry System Operated in a Cryo- Cooler,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DR-O07.

(7) M. Tanaka, K. Takata, R. Sato, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa, N. Zen, M. Ohkubo, “(Invited) Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O01-INV.

(8) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Adiabatic Quantum-Flux-Parametron Cell Library with Minimalist Design and Symmetric Layout,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O06.

(9) F. China, T. Ortlepp, T. Narama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Study of Signal Interface between Single Flux Quantum Circuit and Adiabatic Quantum Flux Parametron,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P28.

(10) N. Tsuji, N. Takeuchi, T. Narama, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Magnetically Coupled Quantum Flux Latch with Large Bias Margins,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P29.

(11) Y. Sasaki, G. Konno, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Improvement of energy efficiency of 64-kb Josephson-CMOS hybrid memories,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P30.

(12) T. Ortlepp, N. Takeuchi, C. Ayala, J. Stark, Y. Yamanashi, N. Yoshikawa,“Performance Analysis of the Adiabatic Quantum Flux Parametron in terms of Sensitivity, Speed and Power Dissipation,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P37.

(13) N. Takeuchi , Y. Yamanashi , N. Yoshikawa, “Energy Efficiency of Adiabatic Quantum-FluxParametron Logic”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P09.

(14) C. J. Fourie , S. Miyanishi , N. Yoshikawa, “Grounding Methods to Reduce Stray Coupling in Multi-Layer Layouts”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P15.

(15) H. Sugata , Y. Yamanashi , N. Yoshikawa, “New Random Number Generation System by Combining Superconducting Physical- and PseudoRandom Number Generators”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P16.

(16) Q. Xu , C. L. Ayala , N. Takeuchi , Y. Yamanashi , N. Yoshikawa , T. Ortlepp, “Design of Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P21.

(17) Y. Yamanashi , S. Nishimoto , N. Yoshikawa, “Single-Flux-Quantum Arithmetic Logic Unit Using Dynamically Reconfigurable Logic Gate”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P23.

(18) H. Suzuki , X. Peng , N. Yoshikawa, “Investigation of Reducing Harmful Effect of Bias Return Current on Ground Plane in Superconducting Integrated Circuits”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P24.

(19) R. Kihara , Y. Yamanashi , N. Yoshikawa, “Power Reduction of Josephson Random Access Memory Using Stochastic Resonance”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P25.

(20) R. Tsutsumi , K. Sato , Y. Yamanashi , N. Yoshikawa, “Improvement of Operation Speed of LR-Biased LowPower Single Flux Quantum Circuits by Introduction of Dynamic Resetting of Bias Currents”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P26.

(21) C. Ayala, N. Takeuchi, Q. XU, T. Narama, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “A Timing and Energy Extraction Approach for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 2M-E-O1.

(22) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Study on energy dissipation in adiabatic quantum-flux-parametron logic at finite temperature”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-01.

(23) Q. XU, C. Ayala, N. Takeuchi, T. Ortlepp, N. Yoshikawa, “Creation of a Logic Simulation Model for Adiabatic Quantum Flux Parametron Logic”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-01.

(24) K. Sano, T. Shimoda, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration and Improvement of Superconducting Time-of-Flight Mass Spectrometry Systems Operated in a Cryo-Cooler”, European Conference on Applied Superconductivity (EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-05.

(25) N. Yoshikawa, “(Invited) SFQ readout circuits for TOF MS systems: Present status and future directions”, Workshop on readout electronics for radiation and particle detectors, Erfurt, Germany, December 20-22, 2015.

(26) T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi , N. Yoshikawa, “Demonstration of 10k gate-scale adiabatic-quantumflux-parametron circuits,” International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383438

(27) Y. Sakashita, T. Ono, Y. Yamanashi1, N. Yoshikawa, “Design and High-Speed Component Tests of an SFQ FFT Processor using the 10 kA/cm2 Advanced Process,” IEEE Trans.I nternational Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383442

(28) Q. Xu , C. L. Ayala , N. Takeuchi , Y. Yamanashi , N. Yoshikawa , T. Ortlepp, “Design of Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic”, IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383446

(29) M. Tanaka, K. Takata, R. Sato, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa, N. Zen, M. Ohkubo, “Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories,” IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383449

(30) C. J. Fourie , S. Miyanishi , N. Yoshikawa, “Grounding Methods to Reduce Stray Coupling in Multi-Layer Layouts”, IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015, . DOI : 10.1109/ISEC.2015.7383461

(31) Y. Sasaki, G. Konno, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Improvement of energy efficiency of 64-kb Josephson-CMOS hybrid memories,” , IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383463

(32) F. China, T. Ortlepp, T. Narama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Study of Signal Interface between Single Flux Quantum Circuit and Adiabatic Quantum Flux Parametron,” IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383483

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