International Conf. of 2013

(1) X. Peng, Y. Shimamura, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa, "(Invited) Design and High-Speed Demonstration of SFQ Bit-Serial Floating-Point Multipliers Using ISTEC 10 kA/cm2 Nb Process, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, A3.

(2) N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Novel Latch for Adiabatic Quantum-Flux-Parametron Logic, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, A5.

(3) Coenrad J. Fourie, X. Peng, A. Takahashi, N. Yoshikawa,"Modelling and calibration of ADP process for inductance calculation with InductEx, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA4.

(4) K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, N. Yoshikawa "Simulation and implementation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron logic, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA7.

(5) T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa, "60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm2 Nb Process," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA8.

(6) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, "Energy Dissipation and Bit-Error-Rate of Adiabatic Quantum-Flux-Parametron Logic with Under-Damped Junctions," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA17.

(7) Q. Xu, Y. Shimamura, N. Yoshikawa, T. Ortlepp, "High-speed demonstration of an integer-based hardware-algorithm using energy-efficient single-flux-quantum circuits,"

(8) International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA22.

(9) A. Takahashi, Y. Yamanashi, N. Yoshikawa, "High-speed measurement of serially biased large-scale SFQ circuits, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA26.

(10) F. China, Y. Yamanashi, N. Yoshikawa, "New superconductive digital magnetometer with sub-flux quantum resolution, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB1.

(11) K. Sato, Y. Yamanashi, N. Yoshikawa, "Novel multiple input single flux quantum merge circuit using serially connected dc-SQUIDs, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB4.

(12) Y. Yamanashi, Y. Tsuga, N. Yoshikawa, "Magnetic field tolerant single-flux-quantum circuit for superconducting sensing system, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB6.

(13) K. Sano, A. Takahashi, Y. Yamanashi, N. Yoshikawa, N. Zen, K. Suzuki, M. Ohkubo, "Design and High-Speed Tests of a Single-Flux-Quantum Time-to-Digital Converter for Time-of-Flight Mass Spectrometry, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, D3.

(14) X. Peng, Y. Sasaki, H. Jin, K. Kuwabara, Y. Yamanashi, N. Yoshikawa, "Demonstration of Fully Functional 64-kb Josephson/CMOS Hybrid Memory," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, H1.

(15) A. Fujimaki, N. Yoshikawa, M. Hidaka, "Research Trend of Superconductor Digital Electronics in Japan, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PL1.

(16) X. Peng, H.Suzuki, Y.Yamanashi, N. Yoshikawa, "A Method to Provide Bias Current for Large-Scale SFQ Circuitsusing Locally Isolated Ground Planes" European Conference on Applied Superconductivity (Eucas2013), Genova, Italy, September 17, 2013, 2P-EL2-02.

(17) N. Takeuchi, Y. Ymanashi, N. Yoshikawa, "Purely reversible quantum-flux-parametron logic," European Conference on Applied Superconductivity (Eucas2013), Genova, Italy, September 17, 2013, 2M-EL-03.

(18) N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi, "Sub-kBT Bit-Energy Operation of Superconducting Logic Devices using Adiabatic Quantum Flux ParametronExtended," Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013), Fukuoka, Japan, September 24-27, 2013, E-4-1.

(19) N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi, "(Invited) Recent Developments on Ultra-Low-Energy Adiabatic Quantum-Flux-Parametron Logic,"26th International Symposium on Superconductivity (ISS 2013), Tokyo, Japan, November 18-20, 2013, FD-12-INV.

(20) K. Sano, Y. Yamanashi, N. Yoshikawa, "Study on the Reduction of the Jitter of an Signe-Flux-Quantum Time-To-Digital Converter for Time-of-Flight Mass Spectrometry," 26th International Symposium on Superconductivity (ISS 2013), Tokyo, Japan, November 18-20, 2013, FD-19.

(21) N. Takeuchi, T. Ortlepp, K. Inoue, Y. Yamanashi, N. Yoshikawa, "Proposal and Implementation of High-Speed Test Circuits for Adiabatic Quantum-Flux-Parametron Gates,"26th International Symposium on Superconductivity (ISS2013),Tokyo,Japan,

(22) November 18-20, 2013, FDP-32.

(23) D. Si, N. Takeuchi, K.Inoue, Y. Yamanashi, N. Yoshikawa, "Yield Analysis of Large-Scase Adiabatic-Quantum-Flux-Parametron Logic:The Effect of the Distribution of the Critical Current," 26th International Symposium on Superconductivity (ISS2013), Tokyo, Japan, November 18-20, 2013, FDP-33.

(24) N. Yoshikawa, "Sub-KBT Bit-Energy Operation of Superconducting Logic: What is the Minimum Energy Bound in the Computation?," East Asia Symposium on Superconductor Electronics (EASSE2013), Taiwan Normal University, Taipei, October 23-26, 2013.

(25) Y. Yamanashi, R. Tsutsumi, N. Yoshikawa, "Circuit Design of Zero-Static Power SFQ Circuit Using Magnetic Flux Biasing," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, O-3.

(26) N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Several Applications Using Quantum-Flux-Latches," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, O-4.

(27) K. Sato, Y. Yamanashi, N. Yoshikawa, "Design and Implementation of a High Sensitive DC/SFQ Converter," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-3.

(28) X. Peng, Y.Sasaki, Y. Yamanashi, N. Yoshikawa, "Improvement of Interface Circuit for Josephson/CMOS Hybrid Memories toward Ground-Current Reduction and Low Power Dissipation," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-4.

(29) S. Nishimoto, Y. Yamanashi, N. Yoshikawa, "New Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-5.

(30) S. Hachiya, Y. Yamanashi, N. Yoshikawa, "Improvement of Performance of a Superconductive Random Number Generator by Optimization of Parameters," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-7.

(31) F. China, Y. Yamanashi, N. Yoshikawa, "Improvement of Slew Rate High-Sensitive Superconductive Digital Magnetomerter ," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-8.

(32) Q. Xu, Y. Yamanashi, N. Yoshikawa, T. Ortlepp, "Imprementation of an Integer-based Hardware-Algorithm in Single-Flux-Quantum Electronics," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-9.

(33) K. Inoue, N. Takeuchi,Y. Yamanashi, N. Yoshikawa, "Design and Test of Basic Cells for Adiabatic Quantum-Flux-Parametron Logic with Magnetic-Shielding Structures," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-10.

(34) Y. Sakashita, Y. Yamanashi, N. Yoshikawa, "Design of an SFQ Butterfly Ciecuit for Signed Number Operation Using the Nb 10 kA/cm2 Josephson Process," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-11.

(35) Y. Sasaki, X. Pen, T. Nishimura, Y. Yamanashi, N. Yoshikawa, "Improvement of Decoders and Data Divers in Terms of Power Consumption for 64-kb SFQ/CMOS Hybrid Memories," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-12.

(36) Y. Muramatsu, K. Sano, Y. Yamanashi, N. Yoshikawa, "Development of Single-Flux-Quantum Multi-Threshold Current Discriminators for m/z-Sensitive Time-of-Flight Mass Spectrometry," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-13.

(37) A. Takahashi, Y. Yamanashi, N. Yoshikawa, "Evaluation of Serially Biased SFQ Circuits Using Floating Ground Plane Structures," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-15.

(38) R. Numaguchi, A. Takahashi, Y. Yamanashi, N. Yoshikawa, "Development of Low-Power Shift-Register Memories Using Josephson-Junction-Biasing SFQ Circuits," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-18.

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